| Summary: | Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Cataloged from student-submitted PDF version of thesis. In title on title page, "[m̳u̳]" appear as lower case Greek letter. === Includes bibliographical references (page 71). === A highly accelerated lifetime test (HALT), is a stress testing methodology for accelerating product reliability that is universally conducted during the engineering development process. In conducting a HALT for circuit components, a burn-in procedure is executed, where the circuit/device is heated to a high temperature for a number of days until finally cooled back to room temperature in order for voltage, current or parameter variations to be compared. When such changes to voltage, cur- rent, or parameters are permanent, no amount of further burn-ins, cool downs or temperature cycling can return the parameter of interest back to its original value it held prior to the burn-in. This is called lifetime-drift and is a problem that circuit simulators do not model. The inability to simulate life-time drift leads to production delays, increasing costs and decreased reliability. In this thesis, I investigated the physics, created a circuit simulation model and implemented an easy-to-use utility for detecting and measuring lifetime drift in 0.18m BiCMOS high sheet resistance (RPH) polysilicon resistors. The circuit model was made using Cadence-Spectre and Verilog-A. The lifetime drift utility was written using Ocean scripting language. === by Anartya Mandal. === M. Eng.
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