Reducing register file size through instruction pre-execution enhanced by value prediction
Main Authors: | Tanaka, Yusuke, Ando, Hideki |
---|---|
Language: | en |
Published: |
IEEE
2009
|
Online Access: | http://hdl.handle.net/2237/13892 http://dx.doi.org/10.1109/ICCD.2009.5413149 |
Similar Items
-
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
by: ANDO, Hideki, et al.
Published: (2010) -
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
by: ANDO, Hideki, et al.
Published: (2009) -
Simultaneous Power Management for Instruction Cache and Register File
by: Kuo-Feng Hsu, et al.
Published: (2007) -
Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures
by: Haijing Tang, et al.
Published: (2013-01-01) -
The optimal size of register file in the superscalar processor design
by: LIN,QING-DE, et al.
Published: (1991)