Designing multimedia extensions for configurable processors
The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon...
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| Language: | en_US |
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2012
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| Online Access: | http://hdl.handle.net/1957/31096 |
| Summary: | The purpose of this thesis is to explore the design of a multimedia extension
Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable
Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a
prototype configurable processor simulator developed at Oregon State University by
John Mark Matson and Dr. Ben Lee. The EM3 ISA uses Single-Instruction Multiple-Data (SIMD) type instructions to improve the performance of multimedia applications on X32V such as MPEG-4.
Two benchmarks based on certain stages of MPEG-4 decompression were
developed to test the initial performance enhancements of EM3. The results of these
benchmark tests indicate a several fold improvement in clock cycles and the number of
instructions executed. This improvement demonstrates the performance increase of
X32V and illustrates the effectiveness of SIMD type multimedia extensions. === Graduation date: 2004 |
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