| Summary: | The wakeup logic in out-of-order superscalar microprocessors is responsible for
resolving the data dependency hazard between instructions. Its performance is critical
because it may prevent the processor to have deeper pipelines or to achieve the highest IPC
(Instructions Per Cycle) possible.
In this thesis, we implemented the circuit and layout for two types of wakeup logic
(CAM-type and RAM-type) used in the modem microprocessors. These two
implementations are simulated extensively using a circuit level simulator - HSPICE, with
full parasitic loads. We, then, made comparison between the CAM-type and RAM-type
wakeup circuits.
From the simulation results, the CAM-type wakeup logic has a better performance than
the RAM-type wakeup logic if a larger number of physical registers is employed by the
processor. The performance impacts caused by varying the other superscalar design
parameters, such as instruction window size and issue width, are not much different for both
types of wakeup logic implementations. === Graduation date: 2003
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