A subranging analog to digital converter using four bit pipepline
This thesis presents the design of a 10 bit Analog to Digital Converter which consists of a 6 bit flash followed by a 4 bit pipeline architecture. The total system is described and the 4 bit pipeline is implemented on a bipolar process. The objective of this research is to provide an alternative app...
Main Author: | Press, Stephen E. |
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Language: | en_US |
Published: |
2013
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Subjects: | |
Online Access: | http://hdl.handle.net/1957/36065 |
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