Netlist Security Algorithm Acceleration Using OpenCL on FPGAs

Netlist Security Algorithm Acceleration Using OpenCL on FPGAs

Bibliographic Details
Main Author: Pelini, Nicholas Michael
Language:English
Published: University of Dayton / OhioLINK 2017
Subjects:
Computer Engineering
Electrical Engineering
OpenCL
netlist
FPGA
DFF
verification
security
Python
gate
ctypes
fan in
fan out
flatten
hash
integrated circuit
acceleration
speedup
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-dayton15018613393180452021-08-03T07:03:46Z Netlist Security Algorithm Acceleration Using OpenCL on FPGAs Pelini, Nicholas Michael Computer Engineering Electrical Engineering OpenCL netlist FPGA DFF verification security Python gate ctypes fan in fan out flatten hash integrated circuit acceleration speedup Integrated circuits continue to grow in number of transistors and design complexity. Production of many of these components are also outsourced to facilities in a number of countries. Therefore, there is a need to ensure all parts within a system are reliable and free from modification. Verification tools must be able to assess circuits down to a gate level but also be scalable to assess complex designs. In response to this problem, an accelerated version of the Integrated Circuit Verification Software is proposed to determine if a manufacturer design is the same as a known, reference design by comparing the two netlists. Optimizations are made to the Python code, and an FPGA hardware accelerated version of the code is created using OpenCL. Results of the OpenCL implementation show an 18x to 24x speedup across various netlists. Additionally, a netlist previously too large for verification tools to run is able to be tested by the OpenCL algorithm. 2017-08-28 English text University of Dayton / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045 http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic Computer Engineering
Electrical Engineering
OpenCL
netlist
FPGA
DFF
verification
security
Python
gate
ctypes
fan in
fan out
flatten
hash
integrated circuit
acceleration
speedup
spellingShingle Computer Engineering
Electrical Engineering
OpenCL
netlist
FPGA
DFF
verification
security
Python
gate
ctypes
fan in
fan out
flatten
hash
integrated circuit
acceleration
speedup
Pelini, Nicholas Michael
Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
author Pelini, Nicholas Michael
author_facet Pelini, Nicholas Michael
author_sort Pelini, Nicholas Michael
title Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
title_short Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
title_full Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
title_fullStr Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
title_full_unstemmed Netlist Security Algorithm Acceleration Using OpenCL on FPGAs
title_sort netlist security algorithm acceleration using opencl on fpgas
publisher University of Dayton / OhioLINK
publishDate 2017
url http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045
work_keys_str_mv AT pelininicholasmichael netlistsecurityalgorithmaccelerationusingopenclonfpgas
_version_ 1719452685776715776

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