IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS

IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS

Bibliographic Details
Main Author: Rajaraman, Bhargavi
Language:English
Published: The Ohio State University / OhioLINK 2009
Subjects:
Computer Science
Register tiling
CLooG
ROSE
TLOG
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518
id ndltd-OhioLink-oai-etd.ohiolink.edu-osu1245123518
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-osu12451235182021-08-03T05:56:35Z IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS Rajaraman, Bhargavi Computer Science Register tiling CLooG ROSE TLOG Tiling is a crucial loop transformation for generating high-performance code on modern architectures to expose coarse grain parallelism in multi-core architectures and to maximize data reuse in deep memory hierarchies. Register tiling improves Instruction Level Parallelism and is critical for these architectures to maximize performance improvements. Tiled loops with parameterized tile sizes facilitate runtime feedback used in iterative compilation and empirical tuning. Chunky Loop Generator (CLooG) is a powerful polyhedral code generator used to generate syntactic code from polyhedral representation of statement domains and data dependences. However, optimizations like loop unrolling and register tiling can only be applied syntactically. We implement register tiling algorithm for perfectly nested loops for rectangular and non rectangular iteration spaces by post processing CLooG ASTs. There are numerous tools like Pluto, TLoG and HiTLoG that use CLooG to generate code after finding various optimizations through polyhedral approaches. An implementation of register tiling in CLooG can give higher performance improvements for generated code. Experimental results using a number of computational benchmarks comparing tiling techniques implemented in CLooG and TLoG, demonstrate the effectiveness of the implemented tiling algorithm. 2009-09-09 English text The Ohio State University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518 http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518 unrestricted This thesis or dissertation is protected by copyright: some rights reserved. It is licensed for use under a Creative Commons license. Specific terms and permissions are available from this document's record in the OhioLINK ETD Center.
collection NDLTD
language English
sources NDLTD
topic Computer Science
Register tiling
CLooG
ROSE
TLOG
spellingShingle Computer Science
Register tiling
CLooG
ROSE
TLOG
Rajaraman, Bhargavi
IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
author Rajaraman, Bhargavi
author_facet Rajaraman, Bhargavi
author_sort Rajaraman, Bhargavi
title IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
title_short IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
title_full IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
title_fullStr IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
title_full_unstemmed IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS
title_sort implementation and evaluation of register tiling for perfectly nested loops
publisher The Ohio State University / OhioLINK
publishDate 2009
url http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518
work_keys_str_mv AT rajaramanbhargavi implementationandevaluationofregistertilingforperfectlynestedloops
_version_ 1719428162766503936

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