AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING

AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING

Bibliographic Details
Main Author: GANDHI, SACHIN
Language:English
Published: University of Cincinnati / OhioLINK 2004
Subjects:
FPGA
FDTD
HPC
hardware implementation
Finite Difference Time-Domain
Reconfigurable High Performance Computing
floating-point implementation
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100550013
id ndltd-OhioLink-oai-etd.ohiolink.edu-ucin1100550013
record_format oai_dc
spelling ndltd-OhioLink-oai-etd.ohiolink.edu-ucin11005500132021-08-03T06:10:00Z AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING GANDHI, SACHIN FPGA FDTD HPC hardware implementation Finite Difference Time-Domain Reconfigurable High Performance Computing floating-point implementation Finite-difference time-domain (FDTD) codes are used in modeling RF signatures and electronic coupling. Despite improvements in large-scale modeling, simulation codes and the acquisition of powerful high-performance computing (HPC) platforms, simulations of such scientific problems require still more powerful computers. The advances in Field-Programmable Gate Array (FPGA) chips and FPGA-based co-processor (FPGA-CP) boards offer the potential for accelerating current and future HPC platforms. Higher capacity FPGAs offer an opportunity for implementing floating point applications, previously infeasible. In this thesis, I have investigated the feasibility of using FPGA-CP acceleration for FDTD simulation. The FDTD method has been chosen for this case study due to its simple computation kernel and abundant parallelism. A floating-point solver for eletro-magnetic simulation has been implemented. Results achieved in this thesis demonstrate the feasibility of high throughput and a good circuit density through the use of architectural features like the 18-bit block multipliers provided by modern-day FPGAs. 2004 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100550013 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100550013 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic FPGA
FDTD
HPC
hardware implementation
Finite Difference Time-Domain
Reconfigurable High Performance Computing
floating-point implementation
spellingShingle FPGA
FDTD
HPC
hardware implementation
Finite Difference Time-Domain
Reconfigurable High Performance Computing
floating-point implementation
GANDHI, SACHIN
AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
author GANDHI, SACHIN
author_facet GANDHI, SACHIN
author_sort GANDHI, SACHIN
title AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_short AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_full AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_fullStr AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_full_unstemmed AN FPGA IMPLEMENTATIN OF FDTD CODES FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_sort fpga implementatin of fdtd codes for reconfigurable high performance computing
publisher University of Cincinnati / OhioLINK
publishDate 2004
url http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100550013
work_keys_str_mv AT gandhisachin anfpgaimplementatinoffdtdcodesforreconfigurablehighperformancecomputing
AT gandhisachin fpgaimplementatinoffdtdcodesforreconfigurablehighperformancecomputing
_version_ 1719432011828953088

Similar Items