PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING

PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING

Bibliographic Details
Main Author: DESAI, ASHISH R.
Language:English
Published: University of Cincinnati / OhioLINK 2006
Subjects:
FPGA
FDTD
Finite-Difference Time-Domain
Cray XD1
Reconfigurable Computing System
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141333144
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-ucin11413331442021-08-03T06:10:56Z PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING DESAI, ASHISH R. FPGA FDTD Finite-Difference Time-Domain Cray XD1 Reconfigurable Computing System The Finite-Difference Time-Domain (FDTD) algorithm is a very powerful tool for modeling and simulation of various electromagnetic problems. The algorithm is computationally intensive but has a simple computation kernel making it suitable for implementation on FPGA co-processor boards of high performance parallel computers. I have redesigned an existing implementation of the FDTD Solver for FPGA co-processor boards of a Cray XD1 system at OSC to substantially improve its performance. This thesis documents the different approaches used and architectural changes made to the existing design to improve its performance. As an alternative approach, I have also designed the FDTD solver using the pre-synthesized floating point library provided by Sandia Labs, USA. The results achieved in this thesis after incorporating all improvements demonstrate that the FDTD Solver design running at 150MHz on the FPGA co-processor board produces results as fast as the software implementation running on AMD OpeteronTM CPUs at 2.4GHz. 2006-04-03 English text University of Cincinnati / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141333144 http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141333144 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic FPGA
FDTD
Finite-Difference Time-Domain
Cray XD1
Reconfigurable Computing System
spellingShingle FPGA
FDTD
Finite-Difference Time-Domain
Cray XD1
Reconfigurable Computing System
DESAI, ASHISH R.
PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
author DESAI, ASHISH R.
author_facet DESAI, ASHISH R.
author_sort DESAI, ASHISH R.
title PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_short PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_full PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_fullStr PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_full_unstemmed PERFORMANCE IMPROVEMENT OF AN FPGA-BASED FDTD SOLVER FOR RECONFIGURABLE HIGH PERFORMANCE COMPUTING
title_sort performance improvement of an fpga-based fdtd solver for reconfigurable high performance computing
publisher University of Cincinnati / OhioLINK
publishDate 2006
url http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141333144
work_keys_str_mv AT desaiashishr performanceimprovementofanfpgabasedfdtdsolverforreconfigurablehighperformancecomputing
_version_ 1719432273549328384

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