High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip

High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip

Bibliographic Details
Main Author: Wang, Mingzhen
Language:English
Published: Wright State University / OhioLINK 2007
Subjects:
tmp_output
ADC
flash ADC
CLK
CMOS
Outputs
comparator
Online Access:http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482
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spelling ndltd-OhioLink-oai-etd.ohiolink.edu-wright11898154822021-08-03T06:16:44Z High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip Wang, Mingzhen tmp_output ADC flash ADC CLK CMOS Outputs comparator Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering, Wright State University, 2007. High-Speed Low-Voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 nanometer (nm) CMOS process. Combining this new comparator design and a proposed pipelined thermometer-Gray- binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital- comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband communication SoC. This architecture has advantages of small silicon area, low power, and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130 nm CMOS process and their experimental results are reported: 1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW of 1-GHz, power of 7.9-mW, and area of 0.022-mm2. 2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of 2-GHz, power of 11-mW. 3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of 34.43-dB, ENOB of 5.4-b, power of 28-mW. An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver, a mixed-signal block-level simulation and verification flow was built in Cadence AMS integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a frequency detection logic show that two tone signals up to 1125 MHz can be detected and discriminated. A notable contribution of this research is that the proposed ADC architecture and the comparator design with dynamic offset suppression and optimization are extremely suitable for future VDSM CMOS processes and make “all-digital” receiver SoC design practical. 2007-09-27 English text Wright State University / OhioLINK http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482 http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482 unrestricted This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.
collection NDLTD
language English
sources NDLTD
topic tmp_output
ADC
flash ADC
CLK
CMOS
Outputs
comparator
spellingShingle tmp_output
ADC
flash ADC
CLK
CMOS
Outputs
comparator
Wang, Mingzhen
High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
author Wang, Mingzhen
author_facet Wang, Mingzhen
author_sort Wang, Mingzhen
title High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
title_short High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
title_full High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
title_fullStr High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
title_full_unstemmed High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip
title_sort high-speed low-voltage cmos flash analog-to-digital converter for wideband communication system-on-a-chip
publisher Wright State University / OhioLINK
publishDate 2007
url http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482
work_keys_str_mv AT wangmingzhen highspeedlowvoltagecmosflashanalogtodigitalconverterforwidebandcommunicationsystemonachip
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