High Speed Clock and Data Recovery Techniques

This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The propos...

Full description

Bibliographic Details
Main Author:	Abiri, Behrooz
Other Authors:	Sheikholeslami, Ali
Language:	en_ca
Published:	2011
Subjects:	CDR Burst-Mode receiver equalization adaptation ADC-based Receiver Blind Sampling CMOS PON 0544
Online Access:	http://hdl.handle.net/1807/30162

id	ndltd-TORONTO-oai-tspace.library.utoronto.ca-1807-30162
record_format	oai_dc
spelling	ndltd-TORONTO-oai-tspace.library.utoronto.ca-1807-301622014-02-21T03:56:50ZHigh Speed Clock and Data Recovery TechniquesAbiri, BehroozCDRBurst-Mode receiverequalizationadaptationADC-based ReceiverBlind SamplingCMOSPON0544This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.Sheikholeslami, Ali2011-112011-12-01T17:38:56ZNO_RESTRICTION2011-12-01T17:38:56Z2011-12-01Thesishttp://hdl.handle.net/1807/30162en_ca
collection	NDLTD
language	en_ca
sources	NDLTD
topic	CDR Burst-Mode receiver equalization adaptation ADC-based Receiver Blind Sampling CMOS PON 0544
spellingShingle	CDR Burst-Mode receiver equalization adaptation ADC-based Receiver Blind Sampling CMOS PON 0544 Abiri, Behrooz High Speed Clock and Data Recovery Techniques
description	This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.
author2	Sheikholeslami, Ali
author_facet	Sheikholeslami, Ali Abiri, Behrooz
author	Abiri, Behrooz
author_sort	Abiri, Behrooz
title	High Speed Clock and Data Recovery Techniques
title_short	High Speed Clock and Data Recovery Techniques
title_full	High Speed Clock and Data Recovery Techniques
title_fullStr	High Speed Clock and Data Recovery Techniques
title_full_unstemmed	High Speed Clock and Data Recovery Techniques
title_sort	high speed clock and data recovery techniques
publishDate	2011
url	http://hdl.handle.net/1807/30162
work_keys_str_mv	AT abiribehrooz highspeedclockanddatarecoverytechniques
_version_	1716648073324658688

High Speed Clock and Data Recovery Techniques

Similar Items