A study on hierarchical register file for loop scheduling in VLIW architecture
碩士 === 逢甲大學 === 資訊工程研究所 === 78 === RISC架構為近年來電腦架構設計的主要趨勢,透過縮短週期時間和簡化導管控制邏輯 ,並由編譯器提供最佳化技巧,達到良好的成本/效益比值。隨著大量處理能力要求 的提升,RISC面臨提高執行率的瓶頸。於是RISC架構將擴展為平行架構,以提高效能 。VLIW電腦架構即為一種單一指令流、多功能單元的平行電腦架構。其特徵為一長指 令包含最大可以平行處理的所有運...
Main Authors: | YANG,WEN-XIN, 楊文新 |
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Other Authors: | XU,HONG-YANG |
Format: | Others |
Language: | zh-TW |
Published: |
1991
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Online Access: | http://ndltd.ncl.edu.tw/handle/00264841206052917346 |
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