A hardware design of variable-rate punctured convolutional decoders

碩士 === 國立交通大學 === 電子研究所 === 78 ===

Bibliographic Details
Main Authors:	LI,HONG-SHENG, 林鴻昇
Other Authors:	WEI,ZHE-HE
Format:	Others
Language:	zh-TW
Published:	1991
Online Access:	http://ndltd.ncl.edu.tw/handle/96424371221160640038

id	ndltd-TW-078NCTU2430146
record_format	oai_dc
spelling	ndltd-TW-078NCTU24301462015-10-13T15:21:05Z http://ndltd.ncl.edu.tw/handle/96424371221160640038 A hardware design of variable-rate punctured convolutional decoders 削短迴旋碼解碼器的硬體架構研究 LI,HONG-SHENG 林鴻昇碩士國立交通大學電子研究所 78 WEI,ZHE-HE 魏哲和 1991 學位論文 ; thesis 100 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子研究所 === 78 ===
author2	WEI,ZHE-HE
author_facet	WEI,ZHE-HE LI,HONG-SHENG 林鴻昇
author	LI,HONG-SHENG 林鴻昇
spellingShingle	LI,HONG-SHENG 林鴻昇 A hardware design of variable-rate punctured convolutional decoders
author_sort	LI,HONG-SHENG
title	A hardware design of variable-rate punctured convolutional decoders
title_short	A hardware design of variable-rate punctured convolutional decoders
title_full	A hardware design of variable-rate punctured convolutional decoders
title_fullStr	A hardware design of variable-rate punctured convolutional decoders
title_full_unstemmed	A hardware design of variable-rate punctured convolutional decoders
title_sort	hardware design of variable-rate punctured convolutional decoders
publishDate	1991
url	http://ndltd.ncl.edu.tw/handle/96424371221160640038
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A hardware design of variable-rate punctured convolutional decoders

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