A design of demultiplexer for MPEG video decoder
碩士 === 國立交通大學 === 電子研究所 === 80 === MPEG是由國際標準組織(ISO) 所開發,為傳輸率在1.5Mbit/s 左右之數位儲存媒介 上的視頻信號及相關音頻信號所制定之壓縮編碼標準。 在本論文中,針對MPEG視頻信號解碼的需求,我們設計了一個解多工器。它的架構 是以一個平行式變動長度解碼器(Parallel Structured Variable-Length Decoder ) 為基礎...
Main Authors: | WANG, SHI-JIE, 王士潔 |
---|---|
Other Authors: | WEI, ZHE-HE |
Format: | Others |
Language: | zh-TW |
Published: |
1992
|
Online Access: | http://ndltd.ncl.edu.tw/handle/70063910671301583717 |
Similar Items
-
A VLSI Realization of DeMultiplexer for MPEG II Video Decoder
by: Wen-Kuo Chu, et al.
Published: (1994) -
Design of MPEG-I Video Decoder
by: Juinn-Kuo Tso, et al.
Published: (1994) -
Related Hardware and Software Design for a MPEG Video Decoding System
by: Wang Tsung Yao, et al.
Published: (1996) -
Design and Implementation of MPEG-II Video Decoder VLSI
by: Lin Chia-Hsing, et al.
Published: (1998) -
Searching and Comparing of Demultiplexer and Decoder in Player
by: 郭明山
Published: (2008)