The Design and Implementation of Motion Estimation in Video Codec

• Main Authors: Juin-Haur Hwang, 黃君豪
• Other Authors: Chein-Wei Jen
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/03075939675075925118

碩士 === 國立交通大學 === 電子研究所 === 81 === Block matching algorithm (BMA) is a widely adopted motion estimation criterion in many standard proposals such as H.261, MPEG, and possibly HDTV. Among the many approaches according to BMA, full search (exhaustive search) is the most computation- intensive one. The advantage is its lower estimation error and regular data access, data flow,and computation sequences. In this thesis we design an architecture for Full Search Block Matching (FSBM) which is cascadable for different speed requirements and expandable for different size of search area. The behavior of this architecture has been simulated using Verilog, and its layout is verified using IRSIM. With tsmc0.8um technology,the die size is 4.8mm$*$5.6mm and the total transistor count is 94555. According to the simulation results of SPICE, the delay time of the critical path is 12.4ns at T=100 oC.