| Summary: | 碩士 === 國立中央大學 === 資訊及電子工程研究所 === 81 === This thesis presents the implementation of a simulator of
shared-memory multiprocessor system for our project UPPER
(User-interactive Parallel Programming EnviRonment), which is
currently developed in NCU. Since the performance of a
specific parallel program is sensitive for program scheduling
techniques, it is important to design and implement a
simulator for parallelizing compilers. Our simulator can help
users or parallelizing compilers to estimate the performance
of a program under the supervision of various program
scheduling techniques. The simulator can simulate arbitrarily
nested parallel loops containing doall and doacross loops in
the form of parallel intermediate codes with synchronization
primitives. The output results of the simulator include the
processor states, such as busy, idle, or communication at
each time stamp, and performance statistics of estimated
execution cost and CPU utilization rates. Finally, several
examples are presented to illustrate the success of our
simulator.
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