| Summary: | 碩士 === 國立臺灣科技大學 === 工程技術研究所 === 81 === In this thesis, we present a VLSI architecture and chip for
motion estimation full-search blocking-matching algorithm
Motion estimation is an important technique for the video image
compression systems. FSBMA is simple and has optimal solution
for motion estimation, but it requires huge amount of
computation. In order to satisfy the requirement of real-time
image compression system, we propose a VLSI architecture for
FSBMA. Such an architecture exhibits both SIMD and systolic
behavior. With small amount of pin-count, a high-performance
FSBMA-based motion estimator is still possibly to be developed.
For tracking range from -8 to +7, the architecture to finish
motion estimation for each 16*16 block requires 1252 cycles. A
VLSI chip has been implemented and fabricated for such
architecture, based on a 0.8 .mu.m CMOS technology by full
custom design methodology. The chip consists of 85736
transistors and has a die size of 0.23 square centimeter. It
is packaged as a 68-pin PGA chip. Testing results have shown
that this chip is functional correct and can operate at 23 MHz.
It is satisfied the requirement of the H.261 and MPEG standard.
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