| Summary: | 博士 === 國立成功大學 === 電機工程研究所 === 82 === In this dissertation, we discuss the problems and a system for
high-level pipelined data path synthesis. The main tasks for
high-level synthesis are scheduling and allocation. Given a
data flow graph, a scheduling program is used for scheduling
each operation to an appropriate step such that the hardware
units can be shared as much as possible. Then, in the
allocation phase, the registers, buses, and function units are
allocated to specific values , transfers, and operations
respectively such that the numbers of connections and
multiplexers are minimum. In Chapter 1, the motivation and
terminologies are introduced . In Chapter 2, we discuss current
scheduling techniques for pipelined data path synthesis. In
Chapter 3, we discuss the essential properties of allocation
problems and a tabu-search based program is presented and
developed for either pipelined and non-pipelined data path
synthesis . In Chapter 4, a synthesizer for nested loop is
presented based on a modified Pipelined List Scheduler and the
tabu- search based allocation program. In Chapter 5,
conclusions are made and future work is identified.
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