| Summary: | 碩士 === 國立交通大學 === 資訊工程研究所 === 82 === Wafer Scale Integration ( WSI ) is a new packaging technology.
Solid State Disk ( SSD ) is an application of Wafer Scale
Integration. A SSD contains hundreds of memory cells. To make
SSD work, memory cells on SSD have to be linked into a linear
array. Any elements of SSD may fail to work. Thus, linking the
good memory cells into a linear array will be an NP-complete
problem. Most contemporary linking algorithms developed are
heuristic algorithms. In this thesis, we propose a twisted
loop- based interconnection design which is more general than
the loop- based design. A graph model which is used to
represent twisted loop-based design is proposed. This graph
model can also represent the loop-based design. Based on this
graph model, we develop a heuristic reconfiguration algorithm
which provides a better harvest rate than Chang and Fuchs. We
also analysis the interconnection path's functional faults. The
faults are classificated into three kinds. Based on this
classification, a diagnosis process which contains self-test
and mutual-test schemes are proposed. A initialization
procedure using the diagnosis results is presented, too.
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