The Study of Neural Expert System for Automatic Diagnosis on Switching System

碩士 === 國立交通大學 === 資訊工程研究所 === 82 === This research attempts to develop a neural network expert system for the diagnosis of telecommunication switching systems. The neural networks were trained with previous faulty situations of switching sy...

Full description

Bibliographic Details
Main Authors: Wen-Lung, Tung, 童文龍
Other Authors: Hsin-Chia, Fu
Format: Others
Language:zh-TW
Published: 1994
Online Access:http://ndltd.ncl.edu.tw/handle/49830638276081929688
Description
Summary:碩士 === 國立交通大學 === 資訊工程研究所 === 82 === This research attempts to develop a neural network expert system for the diagnosis of telecommunication switching systems. The neural networks were trained with previous faulty situations of switching systems and their human diagnostic responses by means of a suitable learning algorithm. We have developed a generalized neural networks system so that by training with a fault diagnosis examples of a particular type of switching system, then the neural networks can be used for diagnosis on this type of switching system. By using binary- value data and having rapid training speed, the Binary Adaptive Networks (BAN) model and Adaptive learning algorithm are selected for the neural network diagnosis system. In addition, some modifications of learning algorithm, based on locally- tuned property of BAN and simulated annealing principle, are proposed to alleviate the local minimum on the network learning problems. The effectiveness of the modifications is presented in the experiments. From the simulation results, while the node number of a BAN is 20000, the correct diagnosis rate of a GTD-5 switching system is above 99% by using the modified learning algorithm. Furthermore, the diagnosis rate on the one bit variation of the training data is between 90% and 95%, and when the variations of training data get up to five bits the diagnosis rate drops between 70% and 90%. As the training data are collected more and more, the diagnosis rate increases quite well. We also have proposed the hardware implementation of BAN by systolic array processor architecture and evaluated the VLSI implementation feasibility of the BAN design.