Design and implementation of a high performance programmable video signal processor

• Main Authors: Chien-Te Wu, 吳建德
• Other Authors: Chen-Yi Lee
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/95096712426292529623

碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, we present a programmable VSP (video signal processor) design targeted to any video algorithm applications. In this design,offering sufficient computational power to cope with algorithm complexity and reducing memory bandwidth to solve I/O bottleneck remain the two key issues to be handled carefully as VLSI technology improves. We also present the circuit techniques and design flow under development in our research Lab. In the design flow, we briefly discuss the design methodology and verification approch under our CAD environment. We then give an in-depth discussion of the circuit design techniques to highlight how a 100MHz clock speed can be encountered. Much effort is focused on both datapath unit and high speed on-chip SRAM which are the key modules of the VSP. In the end, layout strategy, clock distribution and power distribution is given to achieve an area-efficient solution based on TSMC 0.8um CMOS SPDM technology.