Design And Implemention of CMOS Frequency Synthesizer

• Main Authors: Meng-Shiou Wei, 魏盟修
• Other Authors: Dr.Jiin-Chuan Wu
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/69846439206168664575

碩士 === 國立交通大學 === 電子研究所 === 82 === This thesis deals with the design and implementation of a high speed CMOS frequency synthesizer. Frequency synthesizers are widely used in many fields such as wireless communication systems, control circuit, electronic synthesizer, etc. The desired range of operation frequency is from 300MHz to 400MHz. We use 0.8um double-poly double-metal CMOS process, provided by Chip Implementation Center, to design this chip. From the simulated results, we can get a linear region of the voltage controlled oscillator from 300MHz to 400MHz. It will determine the operation frequency of this frequency synthesizer. In order to simplify our design, the programmable counter is modified. But we will focus on the programmable counter in the later chapter to promote the performance. In our measurement, the supply voltage should be descreased to 3 V. We can compare the simulated result with measured result. At last, we will modify the chip to get higher performance.