| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, a novel VLSI architecture is proposed for the
implementation of the well-known full search block matching
motion estimation algorithm. The architecture is based on
efficient data flow design which allows sequential inputs but
performs parallel processing to achieve 100% hardware
efficiency. The architecture mainly consists of four units,
namely memory bank unit, processing unit, delay unit and output
unit. The memory bank unit stores input data in order to save
data loading time. The processing unit does mean absolute
difference between reference data and search data. The delay
unit scales the output partial sum and stores the next
reference data. The output unit adds every row distortion,
identifies the minimum distortion among candidates, and then
sends out the corresponding motion vector. Simulation results
show that, based on TSMC 0.8μm CMOS process technology, clock
speed up to 100MHz can be This implies that the developing chip
can handle many video coding applications based on motion
estimation method.
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