DESIGN AND TEST OF WAVE PIPELINED CIRCUITS

• Main Authors: Shyur, Jui-Ching, 徐瑞卿
• Other Authors: Parng, Tai-Ming
• Format: Others
• Language: zh-TW
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/88989040495749892693

博士 === 國立臺灣大學 === 電機工程研究所 === 82 === Wave pipelining is a new timing technique to boost pipeline rate of a system from two to ten times as fast without additional re- gisters. Current research aims at the implementation, clock sch- emes, and layout issues. This work concentrates on the design flow and test of wave faults. The application is on synchronous CMOS digital systems where latches are used to form multi-stage pipelines. We handle the area-time issues of wave pipelined cir- cuits, achieve error- free design, and two step design flow. The feedback loop problem is also tackled. On the test part of the work, We define the wave fault, propose a statistical and proba- bility fault coverage, and a robust test generation algorithm. As a by-product of our research, we propose the formalism to de- sign lookahead circuits. We show that the iterative network imp- lementation of a FSM can be mapped to a lookahead circuit.