A VLSI Chip for Stage-Pipelined Implementation of Large DFT
碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis a SIMD-Systolic architectures are presentd for computing the Winograd small Fast Fourier Transform algorithms. Based on these architectures,large FFT processors can be developed systemat...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88009712233346896391 |
| Summary: | 碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis a SIMD-Systolic architectures are presentd for
computing the Winograd small Fast Fourier Transform algorithms.
Based on these architectures,large FFT processors can be
developed systematically.Beside,these architectures are of
regular structures and very suitable for VLSI implementation.
Currently,by using 0.8um single-poly double-metal (SPDM) CMOS
technology, a VLSI Processor chip has been designed and
fabricated for one of these SIMD-Systolic architectures.
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