A VLSI Chip for Stage-Pipelined Implementation of Large DFT

碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis a SIMD-Systolic architectures are presentd for computing the Winograd small Fast Fourier Transform algorithms. Based on these architectures,large FFT processors can be developed systemat...

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Bibliographic Details
Main Authors:	Rong-Tyh Wang, 王榮志
Other Authors:	Chen-Mie Wu
Format:	Others
Language:	zh-TW
Published:	1994
Online Access:	http://ndltd.ncl.edu.tw/handle/88009712233346896391

id	ndltd-TW-082NTUST027049
record_format	oai_dc
spelling	ndltd-TW-082NTUST0270492016-02-08T04:06:26Z http://ndltd.ncl.edu.tw/handle/88009712233346896391 A VLSI Chip for Stage-Pipelined Implementation of Large DFT 應用在以分級管線方式計算大點數離散傅利葉轉換之VLSI晶片 Rong-Tyh Wang 王榮志碩士國立臺灣科技大學工程技術研究所 82 In this thesis a SIMD-Systolic architectures are presentd for computing the Winograd small Fast Fourier Transform algorithms. Based on these architectures,large FFT processors can be developed systematically.Beside,these architectures are of regular structures and very suitable for VLSI implementation. Currently,by using 0.8um single-poly double-metal (SPDM) CMOS technology, a VLSI Processor chip has been designed and fabricated for one of these SIMD-Systolic architectures. Chen-Mie Wu 吳乾彌 1994 學位論文 ; thesis 39 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis a SIMD-Systolic architectures are presentd for computing the Winograd small Fast Fourier Transform algorithms. Based on these architectures,large FFT processors can be developed systematically.Beside,these architectures are of regular structures and very suitable for VLSI implementation. Currently,by using 0.8um single-poly double-metal (SPDM) CMOS technology, a VLSI Processor chip has been designed and fabricated for one of these SIMD-Systolic architectures.
author2	Chen-Mie Wu
author_facet	Chen-Mie Wu Rong-Tyh Wang 王榮志
author	Rong-Tyh Wang 王榮志
spellingShingle	Rong-Tyh Wang 王榮志 A VLSI Chip for Stage-Pipelined Implementation of Large DFT
author_sort	Rong-Tyh Wang
title	A VLSI Chip for Stage-Pipelined Implementation of Large DFT
title_short	A VLSI Chip for Stage-Pipelined Implementation of Large DFT
title_full	A VLSI Chip for Stage-Pipelined Implementation of Large DFT
title_fullStr	A VLSI Chip for Stage-Pipelined Implementation of Large DFT
title_full_unstemmed	A VLSI Chip for Stage-Pipelined Implementation of Large DFT
title_sort	vlsi chip for stage-pipelined implementation of large dft
publishDate	1994
url	http://ndltd.ncl.edu.tw/handle/88009712233346896391
work_keys_str_mv	AT rongtyhwang avlsichipforstagepipelinedimplementationoflargedft AT wángróngzhì avlsichipforstagepipelinedimplementationoflargedft AT rongtyhwang yīngyòngzàiyǐfēnjíguǎnxiànfāngshìjìsuàndàdiǎnshùlísànfùlìyèzhuǎnhuànzhīvlsijīngpiàn AT wángróngzhì yīngyòngzàiyǐfēnjíguǎnxiànfāngshìjìsuàndàdiǎnshùlísànfùlìyèzhuǎnhuànzhīvlsijīngpiàn AT rongtyhwang vlsichipforstagepipelinedimplementationoflargedft AT wángróngzhì vlsichipforstagepipelinedimplementationoflargedft
_version_	1718182024557101056

A VLSI Chip for Stage-Pipelined Implementation of Large DFT

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