A VLSI Chip for Stage-Pipelined Implementation of Large DFT
碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis a SIMD-Systolic architectures are presentd for computing the Winograd small Fast Fourier Transform algorithms. Based on these architectures,large FFT processors can be developed systemat...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88009712233346896391 |