The Chip Design of a Parallel Self-Adaptive Fuzzy Inference Engine

• Main Authors: Sheng Fu Yang, 楊勝富
• Other Authors: Jer Min Jou
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/21648053501686332176

碩士 === 國立成功大學 === 電機工程研究所 === 83 === During the past several years, some researches about fuzzy systems have been done, and the hardware implementation of fuzzy inference engine is also developing splendidly. However, to design a self-adaptive fuzzy inference engine chip to execute the task intelligently and efficiently is still to be explored. In this thesis, we present the design and implementation of hardware in the style of 3-stage pipeline and parallel with a tunable knowledge base. Up to 35 rules are inferred in parallel in a time. The memory size is only 62 bytes since a memory-efficient and adjustable rule format as well as rule-generating circuits are introduced. Based on these and a rule weight tuner, our chip posseses the ability of narrowing, widening, moving, amplifying the membership functions and therefore makes the inference process able to be adaptive to the gradual changes of the environment in which it is situated. This chip adopts the Cell-based metholodgy using CCL standard-cell library provided by CIC. The gate counts of this about 36000, and the chip size is 6477.9um*6348.4um. It can yield an inference rate of 467k inferences/sec operating at a clock of 30 MHz.