Digitally redsigned PAM controller and ideal state reconstructor for input time-delay/non-delay systems with nonsynchronous sampling and its implementation

碩士 === 國立成功大學 === 電機工程研究所 === 83 === The digitally redesigned pulse-amplitude modulated (PAM) controller for input time-delay and non-delay systems with nonsynchronous sampling is first developed to improve states discrepancies,...

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Bibliographic Details
Main Authors: Shiaw-Jen An, 安效真
Other Authors: Jason. S. H. Tsai
Format: Others
Language:en_US
Online Access:http://ndltd.ncl.edu.tw/handle/81259952142914225067
Description
Summary:碩士 === 國立成功大學 === 電機工程研究所 === 83 === The digitally redesigned pulse-amplitude modulated (PAM) controller for input time-delay and non-delay systems with nonsynchronous sampling is first developed to improve states discrepancies, so that states at original systems with discrete-time controller will closely match those with continuous-time controller. Also, the ideal state reconstructor of the nonsynchronous sampling case is developed to determine states from the information tion contained in outputs as well as inputs of dynamic systems without building an observer. Furthermore, we present a hybrid suboptimal control of multi-rate multi-loop sampled data systems with the nonsynchronous sampling at outputs ports of both loops. First, we utilize an optimal regional-pole placement technique to find an optimal state-feedback control law for a subsystem connected in the inner loop of the overall system. Next, the redesigned analogue control law is converted into equivalent fast- rate digital control law using the recently developed digital redesign method. Then we modify the digital control law to eleminate the nonsynchronous sampling effect in the inner loop port. Furthermore, we convert the modified digital control system into an equivalent continuous-time model. As a result, the overall continuous-time model can be formulated from the convertered analogue subsystem and the rest of analogue subsystems to be designed. Moreover, following the preceeding step, we find an optimal control law for an overall system and convert it into an equivalent slow-rate digital control law to eleminate the nonsynchronous sampling effect in the outter-loop port and complete the design.