| Summary: | 博士 === 國立成功大學 === 電機工程研究所 === 83 === This work focuses on the automatic placement for integrated
circuits. It covers topics such as printed circuit boards,
power hybrid circuits, and integrated circuits such as standard
cell, gate matrix, and Weinberger designs. In addition, thermal
management technology and reliability prediction also are
considered. All of the algorithms presented in this study are
based on hypergraph structures. For chip level placements, one-
dimensional approaches are presented for different layout
styles. The presented methods can munimize the maximum routing
density of placements, thus obtain high quality results. A
hierarchical placement procedure is developed to take care of
both reliability and wireability for hybrid circuits. Results
indicate that our method can distribute the temperature profile
on the substrate more uniformly and thus improves the system
reliability. Following the reliability improvement the
wireability only degrades slightly. For board level placement,
a placement scheme which couples both wireability and
reliability for convectively cooled boards is presented. An
ordered best-first search algorithm is presented for solving
the two-objective optimization problem. The first solution
obtained by the algorithm has very high quality in system
failure rates. This is very important especially for large-
sized problems, since it infers that one can obtan high
quality solutions with less computation time.
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