The Layout Design of Wafer Scale Integration Solid State Disks
碩士 === 國立交通大學 === 資訊工程研究所 === 83 === Wafer Scale Integration(WSI) uses an entire wafer to implement a digital system. WSI offers many advantages such as lower power consumption, small volume, high speed , and low system costs. However due t...
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ndltd-TW-083NCTU03920672015-10-13T12:53:37Z http://ndltd.ncl.edu.tw/handle/00962077797596692293 The Layout Design of Wafer Scale Integration Solid State Disks 全晶圓積體電子式固態硬碟佈局設計 Yong-Zhong Huang 黃永忠 碩士 國立交通大學 資訊工程研究所 83 Wafer Scale Integration(WSI) uses an entire wafer to implement a digital system. WSI offers many advantages such as lower power consumption, small volume, high speed , and low system costs. However due to large layout area of a wafer, some design issues critical, such as power distribution, and clock synchronization. Another important design issue of WSI design is defect-tolerant abilities. How to bypass defect modules and to harvest as many good module as possible is the key problem for WSI design. In this thesis, the layout design of a WSI Solid- State Disks(SSD) is described. The SSD consisted of identical memory modules on a wafer. The memory modules are interconnected by a loop-based defect-tolerant linear array interconnection. Which offers simple reconfiguration procedure and yet high harvest rate. Verification commands are also implemented in the module so that system testing can be done in a pipelining fashion to reduce the overall testing time. A prototype IC which consists of four modules is fabricated under the support of CIC, NSC. Spice simulations are also used to evaluate three schemes of power distribution. and five schemes of clock distribution. We assume that each module has the capacity of 16Mb, the area of 48mm2, and the current dissipation of 33mA. A 5-inch wafer can contains 196 modules. The simulation results show that the width of the power and ground line must at least 500um to support a stable power supply. Among the five schemes of clock distribution, wide- trunk with separate sub-buffers approach offers the best performance; the clock skew is less than 2.8ns, the rising/ falling time is 2.98ns/2.62ns. The layout design of the WSI SSD is also described. As a single wafer, the SSD design provides 392 MB capacity, and its data transfer bandwidth is estimated at 6 MB/sec. Ming-Feng Chang 張明峰 1995 學位論文 ; thesis 60 zh-TW |
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碩士 === 國立交通大學 === 資訊工程研究所 === 83 === Wafer Scale Integration(WSI) uses an entire wafer to implement
a digital system. WSI offers many advantages such as lower
power consumption, small volume, high speed , and low system
costs. However due to large layout area of a wafer, some design
issues critical, such as power distribution, and clock
synchronization. Another important design issue of WSI design
is defect-tolerant abilities. How to bypass defect modules and
to harvest as many good module as possible is the key problem
for WSI design. In this thesis, the layout design of a WSI
Solid- State Disks(SSD) is described. The SSD consisted of
identical memory modules on a wafer. The memory modules are
interconnected by a loop-based defect-tolerant linear array
interconnection. Which offers simple reconfiguration procedure
and yet high harvest rate. Verification commands are also
implemented in the module so that system testing can be done
in a pipelining fashion to reduce the overall testing time. A
prototype IC which consists of four modules is fabricated under
the support of CIC, NSC. Spice simulations are also used to
evaluate three schemes of power distribution. and five schemes
of clock distribution. We assume that each module has the
capacity of 16Mb, the area of 48mm2, and the current
dissipation of 33mA. A 5-inch wafer can contains 196 modules.
The simulation results show that the width of the power and
ground line must at least 500um to support a stable power
supply. Among the five schemes of clock distribution, wide-
trunk with separate sub-buffers approach offers the best
performance; the clock skew is less than 2.8ns, the rising/
falling time is 2.98ns/2.62ns. The layout design of the WSI SSD
is also described. As a single wafer, the SSD design provides
392 MB capacity, and its data transfer bandwidth is estimated
at 6 MB/sec.
|
author2 |
Ming-Feng Chang |
author_facet |
Ming-Feng Chang Yong-Zhong Huang 黃永忠 |
author |
Yong-Zhong Huang 黃永忠 |
spellingShingle |
Yong-Zhong Huang 黃永忠 The Layout Design of Wafer Scale Integration Solid State Disks |
author_sort |
Yong-Zhong Huang |
title |
The Layout Design of Wafer Scale Integration Solid State Disks |
title_short |
The Layout Design of Wafer Scale Integration Solid State Disks |
title_full |
The Layout Design of Wafer Scale Integration Solid State Disks |
title_fullStr |
The Layout Design of Wafer Scale Integration Solid State Disks |
title_full_unstemmed |
The Layout Design of Wafer Scale Integration Solid State Disks |
title_sort |
layout design of wafer scale integration solid state disks |
publishDate |
1995 |
url |
http://ndltd.ncl.edu.tw/handle/00962077797596692293 |
work_keys_str_mv |
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