| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 83 === The market for cellular radio telephony is expected to
increase dramatically during the 2000's. Service may be
needed for 50% of the population. This is beyond what can be
achieved with the present generation analog cellular
systems. The evolving digital time division multiple access
(TDMA) cellular standards in Europe, North America, and
Japan will give important capacity improvements and may
satisfy much of the improvement needed for personal
communication. In this thesis, a Viterbi decoder was proposed.
The circuit features soft decision decoding, ACS sharing,
and systolic survivor memory management. The control
signal of systolic memory management is very simple and
the wiring is quite regular, not like register exchange
algorithm. Its maximum decoding rate can reach 12.5 MHz, so
it is suitable to IS-54 for error protection of speech. The
speed can be further increased by modifying the datapath of
adder and comparator basing on the requirement area or
speed. The modification does not need to alter the
architecture. The core size of the Viterbi decoder is 3.3(mm)
x 3.6(mm).
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