Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects
碩士 === 國立中央大學 === 電機工程研究所 === 83 === In this thesis, we will present syndrome test for partially scanned MCM. We will do a detail mathematical analysis of syndro me testing. There are two issues in syndrome testing, one is tes t hardware structure another...
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1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78032581382224678611 |
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ndltd-TW-083NCU004420112015-10-13T12:53:41Z http://ndltd.ncl.edu.tw/handle/78032581382224678611 Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects 部份掃描的多晶片模組接線測試 Huang,Shih-Hsien 黃世賢 碩士 國立中央大學 電機工程研究所 83 In this thesis, we will present syndrome test for partially scanned MCM. We will do a detail mathematical analysis of syndro me testing. There are two issues in syndrome testing, one is tes t hardware structure another is to determine the test patterns a nd test length. According to the two issues, We will develope a n algorithm to determine weight, test length, and observation po ints. We will also design a hardware structure for the BIST of partially scanned interconnects based on the results of the anal ysis. Finally, to verify the hardware structure we run Verilog simulation in two test cases, a fault-free case and a faulty cas e. Su,Chau-Chin 蘇朝琴 1995 學位論文 ; thesis 56 zh-TW |
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NDLTD |
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zh-TW |
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Others
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NDLTD |
| description |
碩士 === 國立中央大學 === 電機工程研究所 === 83 === In this thesis, we will present syndrome test for partially
scanned MCM. We will do a detail mathematical analysis of
syndro me testing. There are two issues in syndrome testing,
one is tes t hardware structure another is to determine the
test patterns a nd test length. According to the two issues, We
will develope a n algorithm to determine weight, test length,
and observation po ints. We will also design a hardware
structure for the BIST of partially scanned interconnects based
on the results of the anal ysis. Finally, to verify the
hardware structure we run Verilog simulation in two test cases,
a fault-free case and a faulty cas e.
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| author2 |
Su,Chau-Chin |
| author_facet |
Su,Chau-Chin Huang,Shih-Hsien 黃世賢 |
| author |
Huang,Shih-Hsien 黃世賢 |
| spellingShingle |
Huang,Shih-Hsien 黃世賢 Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| author_sort |
Huang,Shih-Hsien |
| title |
Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| title_short |
Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| title_full |
Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| title_fullStr |
Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| title_full_unstemmed |
Testing and Built-in Self Test Methodology of Partially Scanned MCM Interconnects |
| title_sort |
testing and built-in self test methodology of partially scanned mcm interconnects |
| publishDate |
1995 |
| url |
http://ndltd.ncl.edu.tw/handle/78032581382224678611 |
| work_keys_str_mv |
AT huangshihhsien testingandbuiltinselftestmethodologyofpartiallyscannedmcminterconnects AT huángshìxián testingandbuiltinselftestmethodologyofpartiallyscannedmcminterconnects AT huangshihhsien bùfènsǎomiáodeduōjīngpiànmózǔjiēxiàncèshì AT huángshìxián bùfènsǎomiáodeduōjīngpiànmózǔjiēxiàncèshì |
| _version_ |
1716869155340156928 |