| Summary: | 碩士 === 國立臺灣科技大學 === 工程技術研究所 === 83 === Motion estimation is an important technique for the video image
compress system. For solving it's computationally intensive and
to be real time, a novel two-dimensional SIMD-systolic
architecture has been derived for the FSBMA and a VLSI motion
estimation chip is implemented. In this thesis, we present a
high performance motion estimation processor PCB hardware
design and implementation with using such chip. Also, base on
this hardware, we design a VLSI motion estimation processor
chip. Currently, motion estimation processor is connected to
PC-486 through VESA Local-Bus, operating at 12.5MHZ, computing
10000 motion vector per second. Additional, motion estimation
processor can perform template matching for image recognition.
Template size is 16X16 pixel, and searching range is 32X32
pixel. It takes 100us for template matching computation.
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