| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === Recently, poly-silicon Thin Film Transistors(poly-Si TFT's)
have been extensively studied because of their important
applications in flat-panel display and three-dimentional
integration. Typically, TFT operates with a floating substrate
and the operation bias is about 12V. Moreover, the
characteristics of aTFT cannot be accurately modeled by the
common bulk MOSFET model in SPICE. As poly-Si TFTs technology
matures and more complex analog and digital circuits become
feasible, the lack of an accurate circuit model will be the
major factor limiting circuit integration. It is, therefore,
essential to establish a precise poly-Si TFTs circuit model,
suitable for use in circuit simulations. This work
attempts to develop a physically-based analytical current-
voltage model and an intrinsic capacitance-voltage model of ply-
Si TFTs for circuit simulation. First, we have developed a set
of programs including I-V and C-V models and parameter
extraction methods. The model parameters are extracted from the
experimental data and then substituted back into the developed
models. The accuracy of these models are verified as compared
with experimental data. Then, both models were successfully
implenmented in SPICE. The experiment data used here are
measured from a LCD wafer with p-substrate and top-gate
structure. The gate oxide thickness is 60nm. The channel length
ranges from 5um to 10um. these device models are finally
implemented in the SPICE circuit simulator(version 2G.6)to
predict and analyze the circuit performance of poly-Si TFTs such
as ring oscillator, amplifier, etc.
Device reliability issues are also important in the poly-Si TFTs
due to theimperfection properties in the polysilicon crystals.
It exhibits many defects throughout the material, espically at
the grain-boundary. The general method improving device
performance is to post-process the TFT's with hydrogen plasma
passivation. The method improves device performance but is
unstable under long term electrical stress. By using bias and
temperature stress at the poly-Si TFTs, it is possible to
explore mechanisms of the unstable phenomena such as break of
hydrogn bounds, carrier traping, etc. In the final part of the
work, we try to find the reasons of device degradation by
realizating some stress experiments.
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