A new Precise Interrupts Scheme for Superscalar Processors

• Main Authors: Lay, Jen-Nan, 賴振楠
• Other Authors: Sheu, Jang-Ping
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/66919450181189738694

碩士 === 國立中央大學 === 資訊工程研究所 === 84 === 　　Recently, superscalar technique plays an important role in designing high - performance processors. In order to achieve high performance, out - of - order execution, data, forwarding, and register renaming are necessary techniques in improving instruction - level parallelism of superscalar. However, it is hard to keep precise interrupts when we apply the above techniques. Supporting precise interrupts is a requirement in designing superscalar processor because an interruptible processor should keep precise registers state at any program point. 　　In previous works, three precise interrupts methods were proposed, reorder buffer method, history file method and future file method. We find that future file method gets the most efficiency when it keeps precise interrupts, but future file method suffers from high hardware cost. In this thesis, we propose an efficient precise interrupts scheme to reduce the hardware cost of the future file method. Our method has two major advatages compared to all previous methods. One is that we perform the precise interupts in one clock as the future file method can do. Another one is that we do not need the hardware cost of associate search of register file at register update time.