| Summary: | 碩士 === 國立中山大學 === 電機工程研究所 === 84 === In this thesis, a DRAM circuit was developed for our
simulation. Each subcircuit in the system was discussed. In our
circuit, we design a control circuit for bit-line eqivalence
precharge, it includes an address transition detection circuit
in it to detect the voltage transition on bit-lines. A word-
line buffer was also designed to ensure the precharging
sequence. It latches the add- ress during precharge cycle and
generate the word-lines after precharge. For sensing speed
consideration, we adopted a readout amplifier with current
sensing type, which has higher gain and speed than that with
voltage sensing type. Our circuit also in- cluded a sense-
restore amplifier with barrier transistors, which reduces the
sensing time by about 2.5 ns.
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