| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 84 === PDA is an useful machine for people but the short battery life
of PDA is still a serious problem for users. Therefore, the low
power consumption design is very important for designers. With
considerations of the low power consumption and high performance,
a low power instruction set and architecture are designed.
We analyze the power consumption in an architecture and get a
model to estimate the power consumption in the instruction level.
Following this analysis, we design an instruction set which can
reduce the instruction counts but not increase the complexity of
decoder. Thus, the instruction set combines the advantages of
RISC and CISC to achieve the requirements of low power and high
performance. The switch number is an efficient estimation method
of power consumption in the instruction level. Comparing our
instruction set with ARM's, we can get less switch number about
10\%.
We use the Verilog environment with behavioral level to
verify our design. The input of the simulator is generated by a
code generator which can generate the codes from {\it C} code.
The code generator can reduce the time of writing codes
massively. Therefor, it is a useful tool to reduce the time of
design.
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