| Summary: | 碩士 === 國立臺灣大學 === 資訊工程研究所 === 84 ===
This thesis describes the considerations for applying pass-transistor logic on the implementation of a standard cell library. It is the trend of ASIC (Application Specified Integrated Circuit) design to use HDL (hardwar description language) for flexibility and market time consuming nowadays. By using HDL, ASIC designers can implement circuits without knowing technology in every step of IC design that a full-customed designer has to be familiar with. Cell library plays the role of a basis of generating HDL code into physical layout and makes ASIC designers' ideas come true by simply writing HDL codes.
CMOS has been the mainstay technology for circuit design for decades, and most of the cell libraris are developed in CMOS gate logic. However, several pass-ransistor logic families for macrocell design have been proposed for improving the performance of CMOS circuit. To enhance the performance and to reduce the power consumption is the most essential consideration for the circuit design for the last several years. Pass tansistor has been proven to improve circuit performance and reduce power consumption. To apply pass transistor on standard cell library, there are several considerations that are different fromthat of CMOS in the implementation of a standard cell library.
In this thesis, we have developed a cell library with pass transistor applied, in which designers can design their ASIC by writing behavior-level HDL and simulate the gate-level codes which are transferred from those behavioral-level. HDL codes. Designers utilize gate-level HDL codes for physical ASIC Design, Verilog-in, floorplanning, placement and routing.
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