Power Estimation Techniques and Low Power Design of Double Edge Triggered Flip-Flops
碩士 === 國立臺灣大學 === 電機工程研究所 === 84 ===
Main Authors: | Chen, Ke-Hong, 陳科宏 |
---|---|
Other Authors: | Guo, Si-Yan |
Format: | Others |
Language: | zh-TW |
Published: |
1996
|
Online Access: | http://ndltd.ncl.edu.tw/handle/77905010313488392180 |
Similar Items
-
Power Estimation Techniques and Low Power Design of Double Edge Triggered Flip-Flops
by: Ke-Horng Chen, et al.
Published: (1996) -
Low Complexity and Low Power Designs on Double-Edge-Triggered Flip Flop and Prescaler
by: Shou-Wei Chen, et al.
Published: (2010) -
A dynamic double edge triggered flip-flop for low power applications
by: Lin, Chao-Wei, et al.
Published: (2014) -
A New High-speed and Low-power Double Edge-Triggered D Flip-Flop
by: Yen Chao Wang, et al.
Published: (2004) -
A low-power double-edge triggered flip-flop and an OFDM demodulator for DVB-H receivers
by: Ying-Yu Shen, et al.
Published: (2007)