Development of High Power Factor Single-Phase Switch-Mode Rectifiers

• Main Authors: Hwang, Jonq-Chin, 黃仲欽
• Other Authors: Sheng-Nian Yeh
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/46269221304432198067

博士 === 國立台灣工業技術學院 === 電機工程技術研究所 === 84 === This dissertation presents the design and implementation of the single-phase half-bridge and full-bridge switch-mode rectifiers to yield near-unity power factor and low current distortion on the utility side. The rectifiers can not only function as ac/dc bidirectional power conversion, but also improve the input and output performance. The average duty cycle of the rectifier''s switch state is used to derive the dc link voltage limit and design the parametric values for the input inductance and dc link capacitance. By using the predicted current control, the rectifiers can achieve fast current response and low harmonic distortion. A low-pass filter is introduced in the dc voltage control loop to eliminate the second harmonic component .The delay time caused by the low-pass filter is analyzed and improved. A small-signal model of the power stage is developed to facilitate the root-locus analysis of the control system. The proportional-integral controller can then be designed to assure stable operation and yield the dc voltage dip within acceptable range. Details concerning the determination of controller''s gains are given. The operation of the rectifier is conducted by the combined application of the voltage and current control methods. A single-chip microprocessor is used to implement the system for cost reduction and reliability enhancement. A 1 kW prototype is built to evaluate the performance of the half-bridge and full-bridge rectification. Computer simulation and experiments are given to verify the analysis. The results indicate that under rated operation, the rectifiers possess a power factor of 0.99 and a total harmonic distortion of current of less than 3% on the input side, and fast dc voltage response with zero steady-state error on the output side.