Impact of Set-Associative and Sector on Second-Level Cache

• Main Authors: Lin, Jin-Yi, 林金義
• Other Authors: Shieh Jong-Jiann
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/27008270233024517376

碩士 === 大同工學院 === 資訊工程學系 === 84 === Cache memories have become common accross a wide range of computer implementions. Two-level configurations become even more important in systems. The selection of associativity or sector has significant impact on cache performanceand cost. We use a tracer-driven simulation to examine the effect of a two-levelcache hierarchy in uniprocessors. Because there are a large number of design paramenters to any cache, most of which must be considered in any analysis of the design . In this thesis we focus on set- associativity and sectors to evaluate the miss ratio and bus traffic ratio of different cache size, associativity( degree of associativity, set size) and sectors (subblock).