Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer
碩士 === 國立中正大學 === 電機工程學系 === 85 === As applications demand for a high speed network service, the ATM technology is being considered as a suitable platform. Due to different service scheduling algorithms﹐Cell Delay Variation (CDV) incurred in an ATM Multip...
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ndltd-TW-085CCU004420102015-10-13T12:14:44Z http://ndltd.ncl.edu.tw/handle/22274844112998319191 Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer 非同步傳輸模式多工器之交錯性循環排序的晶片設計 Tsai, Jiann-Shyan 蔡鍵賢 碩士 國立中正大學 電機工程學系 85 As applications demand for a high speed network service, the ATM technology is being considered as a suitable platform. Due to different service scheduling algorithms﹐Cell Delay Variation (CDV) incurred in an ATM Multiplexer will be different. To achieve a good CDV performance, a new scheduling algorithm called Multi_class IRR[1] is proposed. We implement the chip by using CADENCE tools with Compass 0.6 library. We follow the TOP-DOWN methodology to derive the hardware building blocks, we describe each function block by using verilog language and use Synopsys tool to verify the logic design. After performing logic simulation, layout is followed. The designer chip is operated at 33MHz clock rate. The current implementation can support 256 connections with 16 service classes, and support up to 622Mbps link speed. Kim-Joan Chen 陳景章 1997 學位論文 ; thesis 65 zh-TW |
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碩士 === 國立中正大學 === 電機工程學系 === 85 === As applications demand for a high speed network service, the
ATM technology is being considered as a suitable platform. Due
to different service scheduling algorithms﹐Cell Delay Variation
(CDV) incurred in an ATM Multiplexer will be different. To
achieve a good CDV performance, a new scheduling algorithm
called Multi_class IRR[1] is proposed. We implement the chip
by using CADENCE tools with Compass 0.6 library. We follow the
TOP-DOWN methodology to derive the hardware building blocks, we
describe each function block by using verilog language and use
Synopsys tool to verify the logic design. After performing logic
simulation, layout is followed. The designer chip is operated at
33MHz clock rate. The current implementation can support 256
connections with 16 service classes, and support up to 622Mbps
link speed.
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author2 |
Kim-Joan Chen |
author_facet |
Kim-Joan Chen Tsai, Jiann-Shyan 蔡鍵賢 |
author |
Tsai, Jiann-Shyan 蔡鍵賢 |
spellingShingle |
Tsai, Jiann-Shyan 蔡鍵賢 Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
author_sort |
Tsai, Jiann-Shyan |
title |
Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
title_short |
Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
title_full |
Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
title_fullStr |
Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
title_full_unstemmed |
Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer |
title_sort |
chip design of interleaved round-robin scheduling for atm multiplexer |
publishDate |
1997 |
url |
http://ndltd.ncl.edu.tw/handle/22274844112998319191 |
work_keys_str_mv |
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