Chip Design of Interleaved Round-Robin Scheduling for ATM Multiplexer

• Main Authors: Tsai, Jiann-Shyan, 蔡鍵賢
• Other Authors: Kim-Joan Chen
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/22274844112998319191

碩士 === 國立中正大學 === 電機工程學系 === 85 === As applications demand for a high speed network service, the ATM technology is being considered as a suitable platform. Due to different service scheduling algorithms﹐Cell Delay Variation (CDV) incurred in an ATM Multiplexer will be different. To achieve a good CDV performance, a new scheduling algorithm called Multi_class IRR[1] is proposed. We implement the chip by using CADENCE tools with Compass 0.6 library. We follow the TOP-DOWN methodology to derive the hardware building blocks, we describe each function block by using verilog language and use Synopsys tool to verify the logic design. After performing logic simulation, layout is followed. The designer chip is operated at 33MHz clock rate. The current implementation can support 256 connections with 16 service classes, and support up to 622Mbps link speed.