Hardware Design of a Shared-memory Architecture for ATM/Ethernet Switching Subsystems

• Main Authors: Shiau, Wen-Shiuh, 蕭紋旭
• Other Authors: Kim-Joan Chen
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/64517773567389631715

碩士 === 國立中正大學 === 電機工程學系 === 85 === Abstract Design of ATM/Ethernet switching systems has received much attention from R&D organization around the world. This switching system provieds a seamlesstransport platform for interworking tradtional LAN environment with the ATMbackbone. In this thesis, we present an effort for realizing a switchingsubsystem that supports bridging and switching capabilities for transportingdata between Ethernet modules and ATM modules (including ATM/ATM and Ethernet/Ethernet). In this design, we adopt the shared memory structure for the information transfer between Ethernet modules and ATM modules. To support the shared memorystructure, we design a shared memory manager to handle all necessary control and management functions incurred during transferring data from one module toanother. We first describe the related functional blocks for the proposed subsystem. We define associated interfaces and structures for each block. Wedefine control tables to inform modules about data characteristics when involving data transfer. We make use of the translation tables to support thebridging capabilities. We also design a CPU interface for supporting the PVCconfiguration and SVC signaling message transfer. Based on the designed architecture, we describe the logic flow for eachfunctional block, and explain their associated FSMs. We conduct the hardwareimplementation through a Top-Down methodology, which starts with behaviorsynthesis and logic simulation. We simulate and verify the proposed subsystemthrough the following processes: block simulation, FSM simulation, module simulation, and system simulation. We present the related testing process and procedures for each moduleand perform an integrated test for the subsystem. Based on our calculation,throughput of the designed subsystem can reach up to 1056Mbps. To checkwhether the system performs correctly, we analyze worst-case delay performancefor different logic flows. From our simulation, the subsystem can be operatedat 33 MHz speed. Finally, we give some remarks about the development effort of the switchingsubsystem, which includes improvement of hardware design and support of other functionalities.