| Summary: | 碩士 === 國立中正大學 === 電機工程學系 === 85 === Abstract
This thesis concentrates on the hardware design of MX3
Multiplexer. The main function of the MX3 Multiplexer
is multiplexing from 21 E1 signals or 28 DS1 signals to one
DS3 signal. Two steps are involved : the first step is
multiplexes three E1 (2.048 Mb/s) signals to form a DS2 signal
(ME12 multiplexer, G.747) or multiplexes four DS1 (1.544 Mb/s)
signals to form a DS2 signal (M12 multiplexer). The
second step is multiplexes seven DS2(6.312 Mb/s) signals
to form a DS3 (44.736 Mb/s) signals. The MX3
hardware system is equipped with eight low speed units (one for
protection), one switch unit (for the protect switch) and two
high speed units. This thesis special focus on the low speed
unit is the FPGA design of the ME12 and M12
multiplexers, the high speed unit is the FPGA design of
the Switch (8(7) and the application of these elements (UGA-340,
UGA350, 78P7200, LXT332). This thesis also amply
describe the architecture of the MX3 hardware system and
the circuit design of the ME12 and M12 multiplexers.
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