| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 85 ===
The discrete cosine transform (DCT) has been widely recognized as the most effective technique in the area of speech and image/video data compression. It also has been considered as the standard transform coding algorithm for image compression in JPEG (Joint Photographic Experts), MPEG (Motion Picture Experts Group). In this thesis, we purpose a new architecture for the fast computation of a DCT.
A new systolic array is proposed to compute the two-dimensional (2-D) DCT based on row-column decomposition. This architecture uses N2 multipliers to evaluate N×N-point DCT at a rate of one complete transform per N clock cycle. It processes the feature of regularity and modularity, and is thus well suited to VLSI implementation. Compared to existing regular architectures for the 2-D DCT, our method has better throughout performance, smaller area-time, and low communication complexity. The simulation results demonstrate that our architecture have good fixed-point error performance for real image. So the architecture is useful for applications required high throughput rates.
The chip uses 25 MHz image sampling signal frequency. It was design by using cell-based methodology and fabricated with 0.6 μm SPDM technology. The gate count of the chip is about 70000 and the die area is 6150 μm×6150μm.
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