| Summary: | 碩士 === 國立交通大學 === 電子工程學系 === 85 === In this thesis, 1.2V 8-bit and 1.2V 10-bits high-speed CMOS D/
A convertersare designed and fabricated by 0.8-um double-poly
double-metal(DPDM) CMOStechnology and 0.5-um DPDM CMOS
technology, respectively. In these D/Aconverters, the threshold-
voltage compensated current source is used in the two-stage
current array to reduce the linearity error caused by inevitable
current variations of the current sources. In the two-stage
weighted currentarray, only 32 master and 8 slave unit current
sources are required in the8-bit D/A converter, 32 master and 32
slave unit current sources arerequired in the 10 bits D/A
converter. Thus silicon area and stray capacitancecan be reduced
significantly. Experimental results of the 8-bits D/A
convertershow that a conversion rate of 62.5 MHz is achievable
with differential andintegral linearity errors of 0.32 LSB and
0.45 LSB, respectively. The powerconsumption is 15 mW for a
single 1.2V power supply. The rise/fall time is7 ns and the
full-scale settling time to +1/2 LSB is within 16 ns. The chip
area is 2.9 mm x 1.2 mm. The 10-bits D/A converter is under
fabrication, too. A pipelined current-mode Analog-to-Digital
Converter is also proposed and designed in this thesis. No
sample-and-hold circuit is used in the A/Dconverter and the
signal is transmitted freely. Therefore it becomes the keypoint
to generate digital outputs synchronously and reduce the noise
duringthe signal transmission. From simulation results, it is
shown that theproposed A/D converter has 8-bit resolution in
50kHz input bandwidth and theconversion rate is 60MHz.
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