| Summary: | 博士 === 國立交通大學 === 電子工程學系 === 85 === Low power design with high performance is major strend for CMOS
VLSI system design. In mixed mode circuits, the voltage
generations, level conversions, and output analog signals are
essential. This thesis describes the design of power saving
voltage generator, level converter, and buffer amplifier which
are components of mixed mode circuits. The designed components
include: (1) a power efficient charge pump which is used to
generate dual high voltage for RS-232C applications; (2) a
power efficient, high speed TTL-to-CMOS input buffer which is
used in level conversion stage for CMOS digital circuits
applications; (3) a low power CLASS-B output buffer which is
used as data line driver for LCD or FED applications.
Conventional charge pump circuits use a fixed switching
frequency which leads to power efficiency degradation for
loading less than the rated loading. This thesis proposes a
level shifter design that also functions as a frequency
converter to automatically vary the switching frequency of a
dual charge pump circuit according to the loading. The
switching frequency is designed to be 25K Hz with 12 mA loading
on both inverting and non-inverting outputs. The output
voltages of the dual charge pump circuits The output voltages of
the dual charge pump circuits are V+ > 6.5 V and V- < -6 V which
meet the specification of EIA standard for serial communication
(RS-232C applications). The switching frequency is
automatically reduced when loading is lighter to improve the
power efficiency. The frequency tuning range of this circuit is
designed to be from 100 Hz to 25 KHz. In addition, a start-up
circuit is included to ensure proper pumping action and avoid
latch-up during power-up. A non-overlapped two phase clocks and
buffer is used to eliminate short-circuit power dissipation.
The measured results show that the new charge pump has two
advantages: (1) the power dissipation of the charge pump is
improved by a factor of 32 at no load and by 2% at rated loading
of 500ohm; (2) the breakdown voltage requirement is reduced from
19.2V to 17V. Secondly, a separately self-biased differential
amplifier (SSDA) TTL-to-CMOS input buffer is proposed which has
low power dissipation, high operating speed, and its logic
threshold voltage is less sensitive to process and supply
voltage variations. Its logic threshold voltage does not change
when supply voltage is changed from 3.3V to 5V, making it
suitable for 3.3V/5V dual voltage applications. Its simulated
performances are compared with those of inverter, SPSIB, and
CSDA buffers. The SSDA buffer has the lowest power dissipation
for inputs higher than 21MHz. Its operating speed is comparable
to the invert, and much faster than the CSDA and SPSIB buffers.
The measured logic threshold voltage variations due to process
are +-24mV for 5V supply, and +-16mV for 3.3V supply. Its logic
threshold voltage variations due to supply voltage variation
from 3.3V to 5V are within 10mV. With 5V supply, 53MHz input,
and driving another SSDA buffer, its power dissipation is 0.37mW
and delay is 0.45ns. With 3.3 V supply and 47MHz input, its
power dissipation is 0.14mW and delay is 0.51ns. A low power
Class-B output buffer using comparator for driving large
capacitance in flat panel display is presented in this thesis.
Due to the large number of output bufferA low power Class-B
output buffer using comparator for driving large s on a column
driver chip, the quiescent current of the output buffer must be
reduced. A comparator which produces full-swing digital output
is used, in stead of an error amplifier using conventional
output buffer, in the negative feedback path to eliminate
quiescent current in the last output stage. The measured static
current is 54uA. With 5V supply voltage and 600pF load
capacitance, the maximum tracking error voltage is +-8mV, the
output voltage swing is from 0.5V to 5V. The settling time for
4V swing to 0.2% is 8us, which is more than adequate for
driving 1204*1280 pixels LCD panel with 86Hz frame rate.
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