| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 85 === As the computer multimedia is getting prevalent, the need of
fast and high capacity storage media increases dramatically.
Because of its high speed and capacity, CD-ROM is no doubt a
very promising product. However, most of the CD-ROM driving
circuits are implemented by BJT and the cost of BJT is
expensive comparing to MOS. In this thesis, analog front end
circuits using CMOS technology for application in high speed
CD-ROM are proposed. These circuits can be utilized in forty-
folds or higher CD-ROMs and thus can meet the rapid demand in
the future. The AGC acquisition time can be adjusted by
varying external resistors and capacitor of the loop filter
and integrator to satisfy the requirement of different CD-ROM
speed. The whole circuits are verified from post-layout
simulations. The performance summary is as follows: The
bandwidth is 85MHz and the total power consumption is 112mW
(including transimpedance preamplifier, CFOA, open loop
summing amplifier, and AGC) from a 3.3V power supply. The chip
size is about 1.8mm$\times$1.7mm using TSMC 0.6$\mu$m SPDM
CMOS technology.
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