Design and Implementation of Maximum Likelihood Decoders for the BCH Codes

• Main Authors: Chiou, Ming-Cheng, 邱明正
• Other Authors: Chin-Liang Wang
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/11197619353388684993

碩士 === 國立清華大學 === 電機工程學系 === 85 === Error correcting codes are used to protect digital data against errorswhich occur during the transmission through a communication channel. The Bose-Chaudhure-Hocquenghem (BCH) codes have proven to be the best constructivecodes for channels where errors affect consecutive symbols independently. Theconventional algebraic decoding process for the BCH codes can only decode thereceived vector within the designed distance, instead of the actual minimumdistance; this would somewhat limit the performance of th e decoder. Incontrast, the maximum-likelihood (ML) decoding process makes full use of thecode characteristics and channel information, and can reach betterperformance. In this thesis, we propose a new pipelined architecture for ML hard/softdecision decoding of the binary BCH codes. The proposed architecture is basedon coset decoding, where several sub-decoding processes are involved and eachone is realized by vector quantization techniques. It possesses the featuresof regularity and modularity, and is thus suitable for VLSI implementation. Aprototype chip of the proposed decoding architecture has been designed for thebinary BCH (21, 12, 5) code. Simulation results s how that the decoder canprovide a throughput up to 125 Mbit/s under 0.6um CMOS VLSI technology. Thechip area required is about 9.48 * 8.94 mm^2. With a little more area penalty,the throughput of the designed ML decoder can be increased to 875 Mbit/s. Theproposed architecture can also be applied to the ML soft-decision decoder forthe Golay (24, 12) code. As compared to the previous hardware ML decoder, theproposed one has a much higher decoding rate and is more easily realized.